My settings and use of the Arduino DAC are detailed here. Most of the information in these notes is abstracted from the latest SAM3X8E datasheet. In the Atmel datsheet the DAC is described in the Section 44, Digital-to-Analog Converter Controller.
Many of the connections to the SAM3X8E are mulitplexed, and this is the case for the DAC inputs. However it is not necessary to program the PIO controller directly as enabling a DAC channel automatically connects the corresponding input pin to the DAC. The mapping of the Arduino pins to those of the SAM3X8E is given here; so, for example, Arduino DAC0 is connected to PB15.
The DACC uses the master clock frequency divided by two (i.e. 42 Mhz) to carry out the conversions. Once the conversin is started the analog output is available after 25 DACC clock periods.
The DACC has a number of registers that are used to control its operation. Some are read-only (RO), some are write-only (WO) and others are read-write (RW). I now detail how I setup these registers.
Control Register (WO, see section 44.7.1). This has just a single one bit field: SWRST which when set to one causes a software reset of the DAC and can be used to reset the DAC and put it into a known state. The status of the registers after a software reset is:
- The values shown here are obtained using a software reset directly after a system reset.
- The datasheet says that the Analog Control Register should have a value of 0. This is not what I see. Also I see that after using analogWrite() to write to DAC0 or DAC1 the Analog Current Register has the value 0x10A (for this register bits are not used, so 0x1AA and 0x10A are equivalent).
Mode Register (RW, see section 44.7.2). I plan to just use the DAC0 output and to write the values to be converted ans words. With a single output in use I have no need for the TAG filed. For the SDR experiments I will run continuously, although not in free-run mode, and so the sleep mode will be turned off. This determines the following fields of the Mode Register:
As the sleep mode is not used, any startup delay only occurs at the beginning. The startup times for the different field values are given in the datasheet. In the absence of any information I am using the value set when using analogWrite() i.e. 512 DACC clock periods. This is represented by the macro . The DACC clock frequency is the system master clock divided by two, i.e. 42Mhz.
The TRGEN field is a one bit field which determines how the DACC is triggered. When set to zero the DACC is in free running mode. When set to one the DACC is triggered by hardware and the remaining field (TRGSEL) determines which hardware trigger is used. In my experiments I will be triggering the ADC and DAC separately and so using the TIOA output of channel 1 of timer module 0 (TC0) to trigger the DAC. This is represented by the value for the TRGSEL field.
The remaining field to discuss is the refresh field. After the analog voltage resulting from the conversion will start decreasing. To maintain the voltage it is necessary to refresh the channel on a regular basis. This field determines how long this refresh continues. The refresh time is given by
Given the frequency with which samples are written to the DACC the necessary refresh period can be calculated and this used to calculate a REFRESH value. So with a sample frequency, we have
For , we get
The REFRESH field has 8 bits, so can be between 0 and 255. A value of 0 for this field disables the refresh.
Channel Enable Register (WO, section 44.7.3). The first two bits of this register are used to enable channels 0 and 1, writing a 1 in the corresponding bit enables that channel.
Channel Disable Register (WO, section 44.7.4). The first two bits of this register are used to disable channels 0 and 1, writing a 1 in the corresponding bit disables that channel.
Channel Status Register (RO, section 44.7.5). The first two bits of this register are used to disable channels 0 and 1, writing a 1 in the corresponding bit disables that channel. A zero in the corresponding bit position means that the channel is disabled, while a one means that the corresponding channel is enabled. Whether an channel is enabled, or disabled, depends on the latest update of the Channel Enable or Channel Disable Register. Setting an channel bit position in one of these registers overrides what went before.
Conversion Data Register (WO, section 44.7.6). I am using half word mode and so the first 16 bits of the value written is converted; the other 16 bits are ignored.
Interrupt Enable Register (WO, section 44.7.7). The first 4 bits of this register are used to enable the different interrupts. If at all, I will be only using the transmit ready (TXRDY) and end of conversion (EOC) interrupts. Setting the corresponding bit to one enables the interrupt. The other two bits of this register are used for other interrupts, but I am not planning to use these (at the moment).
The DAC has a 4 half-word FIFO. Data for conversion can be written to the FIFO when the TXRDT flag is set. When the FIFO is full the TXRDY flag is cleared.
Interrupt Disable Register (WO, section 44.7.8). Similarly the first 4 bits of this register are used to disable different interrupts. Setting the corresponding bit to one disables the interrupt.
Interrupt Mask Register (RO, section 44.7.9). The bits of this register are used to return the status of each of the interrupts. A zero in the corresponding bit position means that the interrupt is disabled, while a one means that the corresponding interrupt is enabled. Whether an interrupt is enabled, or disabled, depends on the latest update of the Interrupt Enable or Interrupt Disable Register. Setting an interrupt bit position in one of these registers overrides what went before.
Interrupt Status Register (RO, section 44.7.10). The bits in this register indicate whether the corresponding interrupt is active. For the transmit ready interrupt a zero indicates that the DACC is not ready to accept new requests, while a one indicates that the DACC is ready. For the end of conversion interrupt a zero indicates that no conversion has been completed since the previous read of this register. A one indicates that at least one conversion on this channel has been completed since the previous read of this register. Reading this register clears the EOC bit.
Analog Current Register (RW, section 44.7.11). The settings for this register are unclear. In test measurements in the electrical characteristics section (Section 45.9) the following values are used: and . In the absence of other information I will use these values (they give a value of 0x10A if both channels are included).
The remaining three registers can be used to write protect some of the DAC registers. I am not using this facility.
Note that the output range for the DAC is between and of the reference voltage (3.3V unless an external reference is supplied).